An active matrix display device is a display device utilizing TFTs for pixel display drive, has the advantages of light weight, low power consumption, low radiation, low cost and the like, and is one of the mainstream display technologies at present.
An active matrix display device comprises a TFT array substrate. Based on different materials for forming active layers of TFTs, the TFT array substrate may be divided into a variety of types such as hydrogenated amorphous silicon (a-Si: H) type, low-temperature polysilicon (LTPS) type, high-temperature polysilicon (HTPS) type or oxide semiconductor type etc. LTPS TFT array substrates have become one of the research hotspots in the current field due to the advantages of high carrier mobility, high integrate capability, strong anti-interference, etc.
An LTPS TFT array substrate generally comprises a plurality of gate lines along a first direction and a plurality of data lines along a second direction to define and form a plurality of pixel units arranged in a matrix, and the first direction and the second direction are perpendicular to each other. As illustrated in FIG. 1, each pixel unit includes: a pixel electrode 115, a storage electrode 104 disposed beneath the pixel electrode 115, and a TFT disposed at an intersection of a gate line (not shown in the figure) and a data line (not shown in the figure), and the TFT is connected with the pixel electrode 115 and configured to drive the pixel electrode. The TFT includes an active layer 103, a gate electrode 106, a source electrode 110 and a drain electrode 111. In general, the gate electrode 106 is connected with the gate line; the source electrode 110 is connected with the data line; and the drain electrode 111 is connected with the pixel electrode 115.
The method for manufacturing the LTPS TFT array substrate generally comprises: on a base substrate 101 forming a buffer layer 102, patterns of active layers 103 and storage electrodes 104, a gate insulating layer 105, patterns of gate electrodes 106 and gate lines, an interlayer insulating layer 107, source contact holes and drain contact holes, patterns of source electrodes 110, drain electrodes 111 and data lines, a passivation layer 112, pixel electrode contact holes in the passivation layer, a planarization layer 113, pixel electrode contact holes in the planarization layer 113 (communicated with the pixel electrode contact holes in the passivation layer 112), pixel electrodes 115 and a pixel define layer 116 in sequence. The method further comprises: forming a photoresist pattern that shields active layers 103 but exposes the storage electrodes 104, after forming the patterns of the active layers 103 and the storage electrodes 104, to realize the ion doping to the storage electrodes 104, and then removing the photoresist pattern.